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[VHDL-FPGA-Verilog结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 121856 | Author: 于飞 | Hits:

[Post-TeleCom sofeware systemsrs232_send

Description: rs232 vhdl程序 可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
Platform: | Size: 1024 | Author: 李湘宏 | Hits:

[Com PortRS232

Description: FPGA实现RS-232串口收发的Verilog程序,已经调通。-FPGA realization of RS-232 serial port to send and receive the Verilog procedures, Qualcomm has been transferred.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Veriloguart

Description: 用Verilog实现的串口异步通信,适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
Platform: | Size: 1126400 | Author: 王权 | Hits:

[VHDL-FPGA-Verilogrs232

Description: RS232 verilog design
Platform: | Size: 114688 | Author: liuKe | Hits:

[Com Portuart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[Com Portb13c_environment

Description: rs232控制器,实现rs232的环境设置,verilog编写,所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Platform: | Size: 63488 | Author: uknow | Hits:

[VHDL-FPGA-Verilogrs232

Description: dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
Platform: | Size: 121856 | Author: pp | Hits:

[VHDL-FPGA-VerilogRS232

Description: RS232串口通信协议,verilog实现,通过FPGA完全调通。-RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
Platform: | Size: 3072 | Author: dingsheng | Hits:

[VHDL-FPGA-VerilogRS232_pro

Description: RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
Platform: | Size: 2048 | Author: dinsh | Hits:

[Com PortRS232

Description: 很好用的串口通讯程序,已经通过验证,用Verilog语言编写的放心使用了!-Good use of serial communication program has been validated using Verilog language used in the rest assured!
Platform: | Size: 54272 | Author: 宋振丰 | Hits:

[Parallel Portcw3

Description: serial port rs232 in verilog source code
Platform: | Size: 1024 | Author: malkanin | Hits:

[Program docasync_transmitter

Description: 该程序为RS232串口通信的VERILOG程序,在FPGA上已通过验证,在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
Platform: | Size: 1024 | Author: su | Hits:

[VHDL-FPGA-VerilogRS232_project

Description: 串口通讯 rs232 verilog程序,一次接受传送8bits-rs232 verilog project,reciver or trancimiter 8 bits onece
Platform: | Size: 2048 | Author: 王翰林 | Hits:

[Embeded-SCM Developc_FPGA

Description: RS232设计,硬件测试通过,VERILOG实现的,比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
Platform: | Size: 1249280 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilogrs232

Description: 完整的RS232 Verilog源代码,支持波特率可调,支持调试命令,配合串口调试工具,可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
Platform: | Size: 13312 | Author: 弘历 | Hits:

[VHDL-FPGA-VerilogRS232

Description: It s combination logic for UART. edited in verilog-HDL
Platform: | Size: 1024 | Author: kim | Hits:

[VHDL-FPGA-VerilogRS232

Description: It s combination logic for UART. Edited in verilog-HDL.
Platform: | Size: 5120 | Author: kim | Hits:

[VHDL-FPGA-Verilogrs232

Description: 用verilog实现的RS232时序控制,完整可以使用的-RS232 verilog implementation with timing control, you can use the full
Platform: | Size: 1950720 | Author: wangjinghui | Hits:

[Com PortRS232(verilog)

Description: 串口RS232通信程序,包括对串口通信原理的说明。-RS232 serial communication program, including a description of the principles of serial communication.
Platform: | Size: 174080 | Author: 邓民明 | Hits:
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